1. Field of the Invention
The present invention generally relates to a data recovery technology, in particular, to a data recovery apparatus and method by using over-sampling.
2. Description of Related Art
The current image transfer technology may use Transition Minimized Differential Signaling (TMDS) specification or High Definition Multimedia Interface (HDMI) specification for delivery of image signals. According to the TMDS and the HDMI specification standards, a clock signal transferred by a transmitter (Tx) is about 25 to 165 Mhz, and a data transmission rate of an image signal thereof is 10 times of the clock signal. That is to say, in a clock signal cycle, each color channel (including red (R) channel, green (G) channel, and blue (B) channel) bears 10 bits of serial data. Therefore, a receiver (Rx) device employing the TMDS and HDMI specifications must pick and recover the serial data in the color channels by using the relation above.
Among numerous methods for picking data, in order to improve the success ratio of data recovery, data is generally recovered by using over-sampling. FIG. 1 is a block diagram of a conventional data recovery system 100 by using 3× over-sampling. A phase aligning window 130, a phase detection logic circuit 160, a digital loop filter 150, and a phase-aligning finite state machine (phase aligning FSM) 140 may be collectively referred to as digital phase-locked loop (PLL) 170. A PLL 110 receives a clock signal CLK, and multiples the phase of the clock signal CLK by 2.5 times, so as to output 12 multiphase clock signals 112 with different phases to a 3× over-sampler 120.
The 3× over-sampler 120 samples the serial data SD by the multiphase clock signals 112 to generate 12-bit data S[0:11], in which each bit in the serial data SD is sampled three times. In addition, the 3× over-sampler 120 also combines previously sampled last 1 bit of data SP[11] with subsequently sampled first bit of data SN[0] and the 12-bit data S[0:11] to form 14-bit data 122, and outputs the 14-bit data 122 to the phase aligning window 130. The phase aligning window 130 can use a phase aligning signal 142 to pick 12 pieces of over-sampling data from the 14-bit data 122 to form a 12-bit signal Q[0:11], and pick 4-bit signal Q[1] Q[4] Q[7] Q[10] from the 12-bit signal Q[0:11] as recovered data for output.
In addition, the phase detection logic circuit 160 can determine and read the cases such as offset existing between the serial data SD and the clock signal CLK and high-frequency jitter according to the 12-bit data Q[0:11], so as to correspondingly output a phase detection signal 162. The digital loop filter 150 outputs a phase correction recommendation signal according to the phase detection signal 162, that is, a phase forward signal 152 and a phase backward signal 154. Therefore, the phase aligning FSM 140 can generate the phase aligning signal 142 according to the phase forward signal 152 and the phase backward signal 154, so as to drive the phase aligning window 130 to pick 12-bit signal Q[0:11] from the 14-bit data 122, thereby lowering the error probability of data recovery.
FIG. 2 is a schematic view of conventional data recovery by using 3× over-sampling. The transmission time of each bit of data is referred to as one data unit (UI). Referring to FIG. 1 and FIG. 2, based on the above, as the serial data SD carries ten bits of data D0 to D9 in a cycle of clock signal CLK, the 3× over-sampler 120 samples 4-bit data (for example, D0 to D3 in this embodiment) by using rising edges (not shown) of 12 multiphase clock signals 112 at each time, so as to generate 12-bit data S[0:11], and obtains previously sampled last 1 bit of data SP[11] and subsequently sampled first bit of data SN[0] to generate 14-bit data 122.
In general, a data recovery method by using over-sampling frequently employs an odd-time over-sampling technology, because the over-sampled data located centrally (for example, bit signals Q[1], Q[4], Q[7], and Q[10] in the examples above) are theoretically closer to a center of a data eye, and may be output as recovered data. The over-sampled data at two sides (for example, bit signals Q[0], Q[2:3], Q[5:6], Q[8:9], and Q[11] in the examples above) is influenced by Inter Symbol Interference (ISI) or high-frequency jitter, thus being inaccurate.
However, in case that offset between the serial data and the clock signal is too high, or a range influenced by ISI or high-frequency jitter in the serial data is higher than ⅓ data unit (UI), the error probability of the 3× over-sampling technology is correspondingly enhanced. In case of data recovery by using a higher-time over-sampling technology, though the error probability is low, a larger circuit area is required at the cost, and power consumption is increased accordingly. In addition, in an even-time over-sampling technology, there are two over-sampling points that are close to the center of the data eye, and thus how to select an over-sampling point for output is a problem intended to be solved by the even-time over-sampling technology.